Nano-fabrication includes the fabrication of very small structures that have features on the order of 100 nanometers or smaller. One application in which nano-fabrication has had a sizeable impact is in the processing of integrated circuits. The semiconductor processing industry continues to strive for larger production yields while increasing the circuits per unit area formed on a substrate, therefore nano-fabrication becomes increasingly important. Nano-fabrication provides greater process control while allowing continued reduction of the minimum feature dimensions of the structures formed. Other areas of development in which nano-fabrication has been employed include biotechnology, optical technology, mechanical systems, and the like.
An exemplary nano-fabrication technique in use today is commonly referred to as imprint lithography. Exemplary imprint lithography processes are described in detail in numerous publications, such as U.S. Patent Publication No. 2004/0065976, U.S. Patent Publication No. 2004/0065252, and U.S. Pat. No. 6,936,194, all of which are hereby incorporated by reference.
An imprint lithography technique disclosed in each of the aforementioned U.S. patent publications and patent includes formation of a relief pattern in a formable layer (polymerizable) and transferring a pattern corresponding to the relief pattern into an underlying substrate. The substrate may be coupled to a motion stage to obtain a desired positioning to facilitate the patterning process. The patterning process uses a template spaced apart from the substrate and a formable liquid applied between the template and the substrate. The formable liquid is solidified to form a rigid layer that has a pattern conforming to a shape of the surface of the template that contacts the formable liquid. After solidification, the template is separated from the rigid layer such that the template and the substrate are spaced apart. The substrate and the solidified layer are then subjected to additional processes to transfer a relief image into the substrate that corresponds to the pattern in the solidified layer.
Processing techniques using imprint lithography may rely on the presence of a substantially planar underlying substrate or substantially planar underlying layer(s). For example, reliability and ease of manufacturing during layer-by-layer semiconductor device manufacturing may rely on substantially planar substrate topography.
In the context of semiconductor manufacturing, the term planarization may be used to broadly describe two types of processes: topography improvement of a wafer surface after material deposition processes (e.g., planarization of an Inter-Layer Dielectric (ILD); or removal of deposited film to provide material in recessed regions (e.g., Shallow Trench Isolation (STI), Damascene processes, and the like).
Various planarization schemes have been developed include heat and reflow techniques, spin on glass (SOG) processes, and the like. The degree of planarity attainable by current schemes, however, may be limited. For example, one of the commonly used planarization techniques, chemical-mechanical fabrication (CMP) generally has a dependence on the material removal rate based on the pattern density of the material. Areas having high pattern density may have more contact area as compared to areas having a lower pattern density. This may result in more pressure being applied at the low pattern density areas leading to a higher material removal rate within the low-density areas. Low-density areas are planarized first, and then as material is removed at a constant rate, the high-density areas attain local planarization. This may lead to a step-like formation between the high-density and low-density areas and provide a long-range thickness variation within the planarized film. Preventive techniques, such as dummy fill and patterned resist, may be used to reduce the variation in pattern density, however, such techniques increase the complexity of the planarization process.
Contact planarization (CP), an alternative to CMP, provides for a substrate spin coated with a photo-curable material and pre-baked to remove residual solvent. An ultra-flat surface may be pressed on the spin-coated wafer forcing material to reflow and the pressure may be used to evenly spread out material for planarization. The quality of planarization, however, may be compromised by pattern density variation. Spin coating used for fluid distribution is generally expected to be uniform over a substrate. As such, regions with varying densities will generally have the same distribution of fluid. When the material is pressed with the ultra-flat surface, the material tends to flow from high feature density area to low feature density areas. The reflow may be limited due to the high viscosity of the material and/or mobility of the material due to the thin channel formed between the ultra-flat surface and the substrate. Additionally, fluidic forces between the ultra-flat surface and the substrate may cause tensile stress in the fluid film. This stress may be relieved when the ultra-flat surface is removed leading to deterioration in surface planarity.
Moreover, CP generally does not cater for large variations in feature density. For example, if there is a large area in a die with low pattern density, the material may not be able to reflow to fill in the void and thus may affect global planarity. Additionally, CP generally does not account for difference in surface topography of a substrate and/or the ultra-flat surface. For example, when the ultra-flat surface is pressed against the substrate, there may be variations in thickness of the material between them. Use of a very thick film of material may improve mobility of fluid, however, it may be difficult to transfer the same planarity to the substrate as non-uniformity of subsequent material removal processes (e.g., etching, polishing, etc.) may be dominant with thicker films.